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LTC2302/LTC2306
14
23026fa
APPLICATIONS INFORMATION
Figure 2b. Analog Input Equivalent Circuit for
Large Filter Capacitances
Figure 2a. Analog Input Equivalent Circuit
chargingthesample-and-holdcapacitorsduringtheacquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low, the ADC inputs can be driven directly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
Reference
A low noise, stable reference is required to ensure full
performance. The LT1790 and LT6660 are adequate
for most applications. The LT6660 is available in 2.5V,
3V, 3.3V and 5V versions, and the LT1790 is available in
1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions.
The exceptionally low input noise allows the input range to
be optimized for the application by changing the reference
voltage. The VREF input must be decoupled with a 10μF
capacitor in parallel with a 0.1μF capacitor, so verify that
the device providing the reference voltage is stable with
capacitive loads.
If the voltage reference is 5V and can supply 5mA, it can
be used for both VREF and VDD. VDD must be connected
to a clean analog supply, and a quiet 5V reference voltage
makes a convenient supply for this purpose.
Input Filtering
The noise and distortion of the input amplier and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
should be ltered prior to the analog inputs to minimize
noise. A simple 1-pole RC lter is sufcient for many
applications.
The analog inputs of the LTC2302/LTC2306 can be modeled
as a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON) as shown in Figure 2a. CIN gets switched to the
selected input once during each conversion. Large lter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12-bit resolution within the acquisition time (tACQ) if DC
accuracy is important.
When using a lter with a large CFILTER value (e.g., 1μF),
the inputs do not completely settle and the capacitive input
switching currents are averaged into a net DC current
(IDC). In this case, the analog input can be modeled by
an equivalent resistance (REQ = 1/(fSMPL CIN)) in series
with an ideal voltage source (VREF/2) as shown in Figure
2b. The magnitude of the DC current is then approximately
IDC = (VIN – VREF/2)/REQ, which is roughly proportional
to VIN. To prevent large DC drops across the resistor
RFILTER, a lter with a small resistor and large capacitor
should be chosen. When running at the minimum cycle
time of 2μs, the input current equals 106μA at VIN = 5V,
which amounts to a full-scale error of 0.5LSB when using
a lter resistor (RFILTER) of 4.7Ω. Applications requiring
lower sample rates can tolerate a larger lter resistor for
the same amount of full-scale error.
CIN
55pF
RON
100Ω
RSOURCE
VIN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN+, IN–)
C1
23026 F02a
REQ
1/(fSMPL CIN)
VREF/2
RFILTER
IDC
VIN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN+, IN–)
CFILTER
23026 F02b
+
–
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